Tuesday, June 11, 2002, 2:00 PM - 4:00 PM | Room: 287 SESSION 10    Timing Abstraction    Chair: Mark Hahn - Cadence Design Systems, Inc., San Jose, CA    Organizers: Chandu Visweswariah, Narendra V Shenoy    Hierarchical timing verification and re-use of IP blocks require accurate timing abstraction. The first three papers of this session present various approaches to efficient generation of timing abstractions. The last paper applies ATPG and implication techniques to automatically detect multi-cycle paths in sequential circuits.      10.1 Automated Timing Model Generation    Speaker(s): Loa Mize - Synopsys, Inc., Hillsboro, OR    Author(s): Ajay J. Daga - Synopsys, Inc., Hillsboro, OR Loa Mize - Synopsys, Inc., Hillsboro, OR Subramanyam Sripada - Synopsys, Inc., Hillsboro, OR Chris Wolff - Synopsys, Inc., Hillsboro, OR Qiuyang Wu - Synopsys, Inc., Hillsboro, OR      10.2 Timing Model Extraction of Hierarchical Blocks by Graph Reduction    Speaker(s): Cho Moon - Cadence Design Systems, Inc., San Diego, CA    Author(s): Cho Moon - Cadence Design Systems, Inc., San Diego, CA Harish Kriplani - Cadence Design Systems, Inc., San Jose, CA Krishna P. Belkhale - Cadence Design Systems, Inc., San Jose, CA      10.3 Efficient Stimulus Independent Timing Abstraction Model Based on a New Concept of Circuit Block Transparency    Speaker(s): Martin Foltin - Hewlett-Packard, Fort Collins, CO    Author(s): Martin Foltin - Hewlett-Packard, Fort Collins, CO Brian Foutz - Hewlett-Packard, Fort Collins, CO Sean C. Tyler - Hewlett-Packard, Fort Collins, CO      10.4 An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits    Speaker(s): Hiroyuki Higuchi - Fujitsu Labs. Ltd., Kawasaki, Japan    Author(s): Hiroyuki Higuchi - Fujitsu Labs. Ltd., Kawasaki, Japan